This application claims the priority benefit of Taiwan application serial no. 91108649, filed Apr. 26, 2002.
1. Field of the Invention
The present invention relates to a memory device. More particularly, the present invention relates to a structure of a mask read-only memory (ROM) device.
2. Background of the Invention
Mask ROM device comprises the non-volatile characteristics in which memory is retained even the electrical power source is being interrupted. Therefore, this type of memory device is included in many electronic products to maintain a normal operation of xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d for these electronic products. The mask ROM device is the most fundamental type of read-only memory device. A typical mask ROM device uses a channel transistor as the memory cell. To program a typical mask ROM device is accomplished by selectively implanting dopants to the channel region. The xe2x80x9conxe2x80x9d and xe2x80x9coffxe2x80x9d of the memory cell is thus achieved by altering the threshold voltage.
A typical mask ROM device provides a polysilicon word line (WL) crossing over the bit line (BL). The region locates below the word line and between the bit lines serves as the channel region of the memory device. For this type of manufacturing, the storage of the binary digit xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is determined by whether the channel is implanted with dopants. The implantation of dopants to the specified channel region is known as code implantation.
In a conventional mask ROM memory, each memory cell can only store one bit of information. As the increase of the storage capacity of a mask ROM device is being demanded, the field effect transistor that is required for the mask ROM device increases correspondingly. As a result, miniaturizing devices and further increasing the integration of devices can not be accomplished. Moreover, the miniaturization of device to improve the integration of devices is impeded by the slow advancement in manufacturing techniques.
Due to the above problem, it has been proposed to perform the code implantation at both ends of the channel of a memory cell to increase the integration of the device by means of the 1 cell 2 bit method. This 1 cell 2 bit type of storage method requires an implantation of a higher dopant concentration for each individual bit than the dopant concentration implanted for the 1 cell 1 bit type of storage in order to operate the memory cell.
To operate the memory cell A of the above 1 cell 2 bit mask ROM device, a high voltage must be applied to the gate of memory cell A. However, the memory cell B that is contiguous to the memory cell A but is not being operated on is connected to the memory cell A through a same bit line. Being affected by the high dopant concentration implanted in the coding region, the drain region of the memory cell B also senses the current flow, causing the memory cell B to generate a gate induced drain leakage phenomenon (GIDL) and leading to problems of device reliability.
Accordingly, the present invention provides a structure of a mask ROM device, wherein the device can store 2 bit of information in a single cell to increase the integration of the device.
The present invention also provides a structure of a mask ROM device. The device, which comprises a double diffused source/drain region, can lower the gate induced drain leakage.
The present invention further provides a mask ROM device, wherein the operation window of a 1 cell 2 bit mask ROM device is increased, while the second bit effect is decreased.
The present invention provides a mask ROM device. This device includes a substrate, a gate, a double diffused source/drain region that comprises a first doped region and a second doped region, a channel region, a coding region, a dielectric layer and a word line. The gate is disposed on the substrate. The double diffused source/drain region is located in the substrate beside the side of the gate. Moreover, the second doped region is arranged at the periphery of the first doped region. The channel region is positioned between the double diffused source/drain region. The coding region is positioned in the substrate beside the sides of the channel region near the double diffused source/drain region. The dielectric layer is disposed above the double diffused source/drain region, and the word line is disposed above the dielectric layer and the gate.
Additionally, the second doped region is connected to the periphery of the first doped region. The dopant concentration in the first doped region is higher than that in the second doped region.
According to the aforementioned mask ROM device of the present invention, each memory cell can store 2 bit of information. Therefore, the miniaturization of devices to increase the integration of devices can achieve with the existing manufacturing techniques.
Furthermore, the mask ROM device of the present invention comprises a double diffused source/drain region to buffer the high concentration coding implantation through the implanting from the lower concentration doped region at the periphery of the double diffused source/drain region. The gate induced drain leakage is thereby effectively reduced.
Since the mask ROM device of the present invention can effectively lower the gate induced drain leakage, the operation window of a 1 cell 2 bit mask ROM memory device is increased while the second bit effect is mitigated.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.